Chip Design Expert (RTL Design & Verification)

Role overview

Mercor is working with a frontier AI lab on chip design tasks used to train and evaluate AI models. We're looking for experienced RTL design and verification engineers to review these tasks.

Each task is a realistic hardware engineering problem, such as designing or fixing an RTL block or writing a testbench. It comes packaged with a specification, starting files, a reference solution and automated tests.

What you will do

• Review each task end to end: the spec, the starting files, the reference solution and the tests.
• Confirm the task is fair and solvable: the reference solution passes, and everything the tests check can be worked out from the spec.
• Find flaws: ambiguous specs, tests that let wrong designs pass or reject correct ones, leaked answers, and tasks that are easier than they look.
• Judge whether each task is hard enough to challenge today's best AI models.
• Write clear, specific feedback and suggested fixes, and help shape new task ideas.

Who we are looking for

Nice to have: experience with open-source EDA tools (e.g. Icarus Verilog, Verilator, Yosys, cocotb), formal verification, or reviewing benchmarks for AI models.

• 5+ years of hands-on RTL design or verification experience in industry (semiconductor, FPGA, EDA or similar).
• Strong Verilog / SystemVerilog skills, and experience with simulation and testbenches.
• Able to read and reason about Python test code.
• A careful, skeptical reviewer who can explain in writing why a task is broken or too easy.

Details

• Remote and flexible, about 15–20 hours a week.
• $100/hour.
• Starts immediately.